J-K FLIP-FLOP

The J-K FF is the most widely used FF because of its versatility. When properly used it may perform the function of an R-S, T, or D FF. The standard symbol for the J-K FF is shown in view A of figure 3-18.

Figure 3-18. - J-K flip-flop: A. Standard symbol; B. Truth Table; C. Timing diagram.

The J-K is a five-input device. The J and K inputs are for data. The CLK input is for the clock; and the PS and CLR inputs are the preset and clear inputs, respectively. The outputs Q and Q are the normal complementary outputs.

Observe the Truth Table and timing diagram in figure 3-18, views B and C, as the circuit is explained.

Line 1 of the Truth Table corresponds to T₀ in the timing diagram. The PS and CLR inputs are both LOW. The CLK, J, and K inputs are irrelevant. At this point the FF is jammed, and both Q and Q are HIGH. As with the R-S FF, this state cannot be used.

At T₁, PS remains LOW while CLR goes HIGH. The Q output remains HIGH and Q goes LOW. The FF is in the PRESET condition (line 2 of the Truth Table).

At T₂, PS goes HIGH, CLR goes LOW, Q goes LOW, and Q goes HIGH. At this point the FF is CLEARED (line 3 of the Truth Table). The condition of the CLK, J, and K inputs have no effect on the PS and CLR actions since these inputs override the other inputs. Starting at T₃, PS and CLR will be held at HIGHs so as not to override the other actions of the FF. Using the PS and CLR inputs only, the circuit will function as an R-S FF.

Between T₂ and T₃, the CLK input is applied to the device. Since the CLK input has an inverter, all actions will take place on the negative-going transition of the clock pulse.

Line 4 of the Truth Table shows both PS and CLR HIGH, a negative-going CLK, and J and K at 0, or LOW. This corresponds to T₃ on the timing diagram. In this condition the FF holds the previous condition of the output. In this case the FF is reset. If the circuit were set when these inputs occurred, it would remain set.

At time T₅, we have a negative-going clock pulse and a HIGH on the J input. This causes the circuit to set, Q to go HIGH, Q and to go LOW. See line 5 of the Truth Table.

At T₆, J goes LOW, K goes HIGH, and the clock is in a positive-going transition. There is no change in the output because all actions take place on the negative clock transition.

At T₇, when J is LOW, K is HIGH; the clock is going negative, the FF resets, Q goes LOW, and Q goes HIGH (line 6).

With both J and K HIGH and a negative-going clock (as at T₉ and line 7), the FF will toggle or change state with each clock pulse. It will continue to toggle as long as J and K both remain HIGH.

Line 8 of the Truth Table indicates that as long as the clock is in any condition other than a negative-going transition, there will be no change in the output regardless of the state of J or K.

As mentioned at the beginning of this section, J-K FFs may be used as R-S, T, or D FFs.

Figure 3-19 shows how a J-K can be made to perform the other functions.

Figure 3-19. - J-K versatility: A. Using just the PS and CLR inputs; B. Data applied to the J input; C. Both J and K inputs held HIGH.

In view A, using just the PS and CLR inputs of the J-K will cause it to react like an R-S FF.

In view B, data is applied to the J input. This same data is applied to the K input through an inverter to ensure that the K input is in the opposite state. In this configuration, the J-K performs the same function as a D FF.

View C shows both the J and K inputs held at 1, or HIGH. The FF will change state or toggle with each negative-going transition of the clock just as a T FF will.

Now you can see the versatility of the J-K FF.

Q.27 What type of FF can be used as an R-S, a T, or a D FF?
Q.28 What will be the output of Q if J is HIGH, PS and CLR are HIGH, and the clock is going negative?
Q.29 Assume that K goes HIGH and J goes LOW; when will the FF reset?
Q.30 What logic levels must exist for the FF to be toggled by the clock?
Q.31 What two inputs to a J-K FF will override the other inputs?
Q.32 How is the J-K FF affected if PS and CLR are both LOW?