Delay Equalization Circuits

TM 11-5805-424-15/NAVELEX 0967-220-9010/TO 31W2-2G-41

resistor, and resistor R4 is the collector load

a linear output signal to the timing output terminals.

resistor. Resistor R12 and capacitor C5 and

Diode CR1, in series with the base-emitter junction of

resistor R13 and capacitor C6 provide additional

transistor Q5, compensates for the diode characteristics

filtering of the dc power supply voltages.

of the junction. Diode CR3 limits transistor Q5 collector

voltage to +6 volts; resistors R8 and R9 provide for

(2) Output from transistor Q1 emitter is applied,

proper biasing of transistor Q5; and resistors R10 and

through a delay capacitor in the receive filter, to

R11 provide for proper biasing of transistor Q6.

impedance-matching emitter follower Q2. With

EQUALIZER switch S1 at OUT, the delay

5-18. Delay Equalization Circuits

capacitor is shorted out so no delay is

introduced into the received signal.

With

EQUALIZER switch S1 at COMP, the output.

a. General. The delay equalization circuits provide

from the collector of transistor Q1 (through

varying amounts of delay for the different input

coupling capacitor C2 and resistor R5, through

frequencies of the received fsk signals, so that the

resistor R8) is applied to transistor Q2; at the

output from the delay equalization circuits contains the

same time, the output from the emitter of

same amount of delay and, hence, no delay distortion

transistor Q1 is applied through the delay

for all frequencies in the appropriate channel received.

capacitor in the receive filter to transistor Q2.

The schematic diagram shown in figure 8-25 represents

This parallel arrangement provides a small

the circuits employed in the MX-7379/G only, employing

amount of delay over a relatively wide

a separate delay equalizer PC card (PC80034230; assy

frequency band. With EQUALIZER switch S1 at

A25A3) and switching circuit; for all other MX-73(*)/G's,

ADJ, DELAY ADJ resistor R6 is substituted for

the PC card is not used. For the MX-7380/G, MX-

fixed resistor R8, providing an adjustment of the

7383/G, and MX-7384/G, MX-7385/G, a switch selection

delay range.

circuit is provided to vary the amount of delay (A, fig. 8-

(3) When FREQ switch S2 is at B, a parallel-tuned

26). For the MX-7372/G through MX7378/G, and MX-

circuit is added, in parallel with the delay circuits

7381/G and MX-7382/G (B, fig. 8-26), no selection is

described in (1) and (2) above; this arrangement

provided; only a fixed amount of delay is available.

provides a larger amount of delay over a

Discussion of delay equalization used with the MX-

narrower frequency band.

7379/G is given in b below. Operation of the other types

is self-evident when analyzed from the overall delay

(4) The delayed signal is applied through transistor

equalization discussion given in b below.

Q2 to another delay circuit that is identical with

that described in (1), (2), and (3) above. The

b. Circuit Operation (fig. 8-25).

delayed signal, amplified by transistor Q4, is

(1) The received input signals are applied to

applied through coupling capacitor C4 to the

paraphase amplifier Q1, which provides two

remainder of the receive circuitry. Resistor R10

outputs that are equal in frequency and

is the emitter-biasing resistor, and resistor R11

amplitude and 180° out of phase with each

is the collector load resistor for transistor Q4.

other. Capacitor C1 is the coupling capacitor,

and resistors R1 and R2 provide operating bias

for transistor Q1. Resistor R3 is the emitter load

Section IV. LOGIC ANALYSIS

TRANSMITTER DATA INPUT terminals and INPUT

5-19. Transmit Data

SELECT switch 1A1S5 (switch at DATA) to differential

(fig. 8-5)

amplifier DIA-1. Differential amplifier DIA-1 provides

two output signals that are 180°out of phase with each

a. Input data is applied through ORDER WIRE

SEND jack 1A1J1 (no plug inserted) from the

5-17