Send Timing

TM 11-5805-424-15/NAVELEX 0967-220-9013/TO 31W2-2G-41

applied from pin 3 to the output amplifier circuit in the

other to AND gates GAS-1 and GAS-2 in the common

transmit output and carrier alarm module (para 5-24)

alarm module (para 5-24) and to AND gates GAI-1 and

through OUTPUT LEVEL ADJ resistor 1A1R6. The vf

GAI-2 in the crystal oscillator and oven regulator

signal from the output amplifier circuit is coupled

module.

through transformer 1A1T2 to the BALANCED XMTR

(1) When the transmit data input is in a mark

CARRIER OUTPUT terminals at the rear of the unit.

condition, differential amplifier DIA-1 output (negative)

OUTPUT switch 1A1S7 controls the output impedance;

enables AND gate GAI-1, and the positive output inhibits

with the switch at 600 , resistor R38 and diodes CR12

AND gate GAI-2. Thus, the output of mark oscillator

and CR13 are placed across the secondary of

OSC-1 is fed through AND gate GAI-1 and through the

transformer 1A1T2 to provide an output impedance of

hidden OR gate to inverter IN-1 in the MX73(*)/G

600 ohms.

With the switch at 50K , the output

countdown assembly A18A2-A32A2.

impedance is 50,000 ohms.

(2) When the transmit data input is in a space

condition, differential amplifier DIA-1 output enables

5-20. Send Timing

AND gate GAI-2, and inhibits AND gate GAI-1. Thus,

output of space oscillator OSC-2 is applied through AND

gate GAI-2 and the hidden OR gate to IN-1, Diode

Bit-timing signals are supplied to the external

A16CR1 maintains the oscillator output signal level

transmitting equipment in either phase (strap selected).

between 0 and -6 volts.

Initial timing signals (clock) may be provided by an

internal 1.2288 megacycle (mc), crystal-controlled

b. The frequency-determining module (fdm)

oscillator (a below) or may be supplied from an external

countdown assembly may contain three bistables (fig. 8-

source at bit-rate (b below).

24), or it may use only one or two bistables (figs. 8-22

a. Internal Clock. Output of the 1.2288-mc, crystal

and 8-23, respectively, depending on the output mark

oscillator (fig. 8-5) is applied through inverters IN-20

frequency and space frequency desired for the particular

(which isolates the crystal oscillator) and IN-21 (which

configuration. Where an fdm countdown assembly is

provides the proper phase of the oscillator signal; to a

not used, the mark and space frequencies are routed

three-stage binary counter. Bistables FFC-13, FFC-14,

through pin 20 of connector A18P1-A32P1 directly to the

and FFC-15 divide the 1.2288-mc input frequency by 8,

64 divider module. (Pin 20 is opened when an MX-

to provide timing signals of 153.6 kilocycles (kc) to the

73(*)/G countdown assembly is used.)

variable-control oscillator module. With the variable-

c. The countdown assembly and the ,64 divider

control oscillator module strapped for INT CLOCK, the

assembly count down the mark frequency and the space

153.6-kc signal from bistable FFC-15 is inverted by

frequency from mark oscillators OSC-1 and space

inverter IN-15, and applied to a second three-stage

oscillator OSC-2, respectively, to the required channel

binary counter (bistables FFC-10, FFC-11, and FFC-12).

frequencies. A positive input trigger is required by each

Output from each bistable, plus the output of FFC-15, is

bistable FFC-1 through FFC-9. The output square wave

applied to separate contacts of BAUD RATE switch

of bistable FFC-9 (either at the mark or space

1A1S2, which selects the output of one of the bistables,

frequency) is applied to phase-splitting amplifier PSA-1,

depending on the operating rate desired. With BAUD

which provides a polar square-wave output to transmit

RATE switch 1A1S2 at 1200,. the 153.6-kc signal from

filter FL2. Transmit filter FL2 converts the square-wave

bistable FFC-15 is applied to the 128 divider-A module.

input to a vf sine-wave signal and applies it from pin 7 to

At 600, 300, and 150 BAUD RATE switch 1A1S2 selects

amplifiers AM-3 and AM-4 in the 64 divider module.

and applies the output of FFC-10(76.8kc), FFC-11 (38.4

Amplifiers AM-3 and AM-4, together with an attenuation

kc), and FFC12 (19.2 kc), respectively, to the 128

pad in transmit filter FL2. allow for enough filter

divider-A module. The selected frequency from BAUD

bandwidth at all operating frequencies, particularly at the

higher channels. The final vf output signal from the

transmit filter (after any necessary attenuation) is

Change 5

5-18