ARMY  TM  5-6675-238-14 MARINE CORPS TM 08839A-14/1 (4) SPU basic control logic test. Before the vari- ous  functional  segments  in  the  SPU  can  be  self-tested,  it is  necessary  to  test  the  basic  logic  in  the  SPU  that controls the serial data bus circuitry. This basic logic includes registers and steering logic for self-test tape data. It also includes address decode logic and parity check logic which is common to all of the SPU func- tional  segments.  By  reading  known  address  and  parity data from the self-test tape and comparing that decoded parity and address to the expected parity and address, the SPU basic control logic is determined to be operat- ing properly, or else a failure has occurred, If the SPU basic control logic is operating properly, the self-test tape is advanced to the first functional segment test. If a failure occurs in the SPU basic control logic, a special code is displayed on the FAILURE/ACTION indicator. closer  self-test  is  functionally  illustrated  in  figure  FO-11 and is contained on logic no. 3 electronic component assembly A3. The tape reader supplies data that is used for all control functions. The 2.4-kHz clock is gated on or off by BITE circuitry control.      The                          differential line drivers are first tested statically  with the clock off. Next the clock is gated on and the        differential line driver outputs are checked. The clock pulses should appear  on  all  output  lines,  The  clock  circuitry  is checked separately. The clock is tested for both correct amplitude  and  correct  frequency. (6) Serial dirts bus loop closer self-test.  The  serial data  bus  loop  closer  self-test  is  functionally  illustrated in figure FO-12 and is contained on logic no. 1 elec- tronic component assembly Al and logic no. 3 elec- tronic  component  assembly  A3.  The  tape  reader  sends the specific address to activate the serial data bus loop- around  circuitry.  The  self-test  tape  data  is  used  to duplicate the normal computer serial data bus data and control functions. BITE circuitry for the serial data bus loop-around circuitry are the self-test tape to serial data bus conversion logic,   input  data  parity  generation, check and store, and compare logic. The address word from  the  self-test  tape  is  stored  and  decoded,  then parity is checked. If parity is correct, a data envelope signal and a clock signal are received from the self-test tape. The data envelope signal causes the address word to be shifted out of the storage register. The address word is inverted as it shifts out and back in simulta- neously. Parity is checked against the expected parity of the inverted address. If the parity of the output data from the address/data line receiver is opposite to the parity of the original address word, the serial data bus loop-around circuitry is considered good. However, if the serial data bus fails to perform certain tests, then the time-out counter is not reset causing a serial data bus failure indication. BITE circuitry then goes on to the next functional test. (7) Teletypewriter  control  logic  self-test.  The  tele- typewriter control logic self-test is functionally illus- trated in figure FO-13 and is contained on logic no. 1 electronic component assembly Al. BITE circuitry for the  teletypewriter  circuitry  self-test  are  the  self-test tape  to  DMA  control  and  compare  logic.  The  tape reader  sends  the  specific  address  that  activates  the teletypewriter circuitry in the SPU. A universal asyn- chronous  receiver/transmitter  (UART)  module  is  used for control of the teletypewriter. The UART normally communicates  with  the  computer  via  the  computer data bus. However, for SPU built-in-test, the DMA data lines that are common to the computer data bus are to communicate  with  the  UART.  After  the  teletypewriter circuitry has been activated via an address word from the self-test tape, a data word from the tape is loaded into the UART send register. Next, a command word from the tape is loaded into the UART control register. This  control  word  initiates  the  UART  send/receive cycle. On the send cycle the data in the send register is converted  to  serial  form  and  given  start  code,  stop code, and timing characteristics in accordance with the type of teletypewriter involved. For the built-in test, the serial data to the teletypewriter is wrapped back as an  input  to  the  serial  data  from  the  teletypewriter. Hence,  a  total  SPU  teletypewriter  circuitry  check  is made without having to connect the teletypewriter to the SPU. The SPU teletypewriter self-test compares the parallel  data  from  the  UART  receive  register  to  the parallel data from the send register. If the comparison checks good, the SPU teletypewriter circuitry is consid- ered good and the tape reader is advanced to the next SPU self-test. If the test is not successful, the FAIL- URWACTION  indicator  reads  out  the  fault  and  the tape reader is halted. If the test is successful, the BITE circuitry  will  instruct  the  operator  to  hook  up  the teletypewriter.  Echo  checking  of  any  character  entered from the keyboard can now be made ensuring that the teletypewriter and the SPU current loops are good. If this echo-check mode is good, the next BITE test is started by pressing and repressing the SPU SELF TEST switch. (8) Digital/resolver and   digital/synchro   loop closer self-test.  The digital/resolver and digital/synchro loop  closer  self-test  is  functionally  illustrated  in  figure FO-14 and is contained on logic no. 1 electronic com- ponent  assembly  Al.  BITE  circuitry  for  the  digital/ resolver and digital/synchro loop closer self-test are the self-test  tape  to  serial  data  bus  conversion  logic,  refer- ence generator, amplifier and phase shift test circuit, precision amplifier-ratio test circuit, and overall test good  or  no  good  circuit.  The  tape  reader  sends  a specific  address  to  activate  the  digital/resolver  and digital/synchro   loop   closer   circuit.   Then   the   tape reader sends the specific 14-bit angle which is used for the self-test. Since the self-test tape data is made to look  like  the  computer  serial  data  bus,  the  self-test exercises the loop closer circuitry in the same way as it 6-11