ARMY  TM  5-6675-238-14 MARINE  CORPS  TM  08839A-14/1 Bit  0  will  change  from  false  to  true  logical  state  when- ever   bit   1,   2,   or   3   change   from   the   false   to   the   true state,   Bit   0   will   change   back   to   the   false   state   on   an INP  status  command. (9)   The   UART   serial-to-parallel   or   parallel-to- serial   timing   takes   place   after   the   proper   command word  has  been  received.  On  the  send  to  teletypewriter cycle,  the  data  in  the  send  register  is  converted  to  serial form  and  given  start  code,  stop  code,  and  timing  char- acteristics  in  accordance  with  the  type  of  teletypewriter involved.   The   SPU   timing   is   for   a   five   level   Baudot teletypewriter.   On   the   receive   from   teletypewriter   cy- cle,  the  serial  output  from  the  teletypewriter  is  accumu- lated   in   the   receive   register   after   having   the   start   and stop codes stripped off. k.  Built-In  Test.   The  SPU  contains  circuitry  for self-test,  During  self-test,  the  SPU  must  be  disconnected from  all  external  devices  except  the  tape  reader.  Three cables   that   normally   connect   to   the   computer   must   be looped   back   and   connected   to   test   connectors   on   the SPU.  The  buffer  unit  cable  is  not  looped  back  for  self- test   until   the   SPU   FAILURE/ACTION   indicator   indi- cates  to  do  so.  When  the  SELF  TEST  switch-indicator is  activated,  the  SPU  bit  circuitry  and  FAILURE/ ACTION  indicator  are  enabled.  In  the  self  test  mode  of operation,   the   tape   reader   is   controlled   by   the   SPU BITE   circuitry   and   the   self-test   tape   data   is   made   to look  like  computer  serial  data  bus  address  and  data information.   Once   the   SELF   TEST   switch-indicator   is activated,   the   self-test   tape   is   read   automatically.   Each functional  segment  of  the  SPU  circuitry  is  tested  by  a corresponding  segment  of  tape  information.  If  a  failure occurs   at   any   test   segment,   the   tape   reader   will   stop. The   address   at   which   the   failure   occurred   will   be displayed   as   a   two   digit   number   on   the   FAILURE/ ACTION   indicator.   When   the   computer/buffer   unit circuitry  internal  to  the  SPU  has  been  tested  without  a failure  occuring,  the  tape  is  not  automatically  restarted. Instead,  a  special  code  is  displayed  on  the  FAILURE/ ACTION  indicator.  This  code  instructs  the  operator  to deactivate  SPU  and  connect  the  buffer  unit  cable  to  a test  connector  on  the  SPU.  Once  connected  the  opera- tor  again  turns  SPU  on  and  then  reactivates  the  SELF TEST   switch-indicator.   This   action   causes   the   tape   to restart   and   the   buffer   unit   self-test   is   performed.   All tests   except   the   one   requiring   manual   intervention   are fully   automatic   and   cause   the   tape   reader   to   continue after  each  test  has  been  completed  and  no  failures  have occurred. (1) Tape  reader  control  logic  self-test.  The  tape reader  control  logic  self-test  is  functionally  illustrated  in FO-10  and  is  contained  on  logic  no.  1  electronic  com- ponent   assembly   Al,   The   tape   reader   data   is   made   to look   like   the   computer   serial   data   bus.   Therefore   all computer   serial   data   bus   control   and   data   functions performed   during   normal   computer   operation   will   be performed  by  the  tape  reader.  The  tape  reader  is  tested by   monitoring   in   the   SPU   that   the   proper   control signals   have   been   sent   to   the   tape   reader   and   that proper  data  has  been  read.  This  is  based  upon  known data  existing  on  the  self-test  tape,  Once  the  tape  reader has  been  established  as  good,  the  next  data  on  the  self- test  tape  is  used  to  load  a  16-bit  register  in  the  SPU. Three   bits   of   each   tape   reader   character   are   used   to control  the  set  up  and  timing  of  the  register,  while  the next  four  bits  are  used  as  data  to  be  loaded,  Therefore, four  ASCII  characters  are  required  to  load  the  register. The   parity   bit   in   each   ASCII   character   is   checked.   If parity   is   incorrect,   the   test   is   halted   and   the   PARITY ERROR  indicator  is  lighted  on  the  SPU  panel.  After  the four  ASCII  characters  have  been  loaded  into  the  16-bit register,   they   are   verified   to   be   correct   by   comparing the   loaded   data   to   the   known   value   that   should   exist based  upon  the  data  on  the  self-test  tape.  Then  the  16- bit   data   word   is   recessed   by   special   SPU   built-in-test ) equipment   (BITE   circuitry.   This   BITE   circuitry   for- mats  the  data  and  generates  timing  signals  so  that  the output   of   the   circuitry   looks   like   the   computer   serial data  bus.  This  serial  data  bus  information  is  sent  to  the serial  data  bus  control  logic  to  control  the  testing  of  all other  functional  segments  of  the  SPU. (2) FAILURE/ACTION indicator test.  Before do- ing   any   self-testing,   the   FAILURE/ACTION   indicator should  be  checked  to  ensure  that  it  is  operating  prop- erly.  This  is  done  by  pressing  the  LAMP  TEST  switch, This  switch  forces  the  FAILURE/ACTION  indicator  to sequence  through  30,  20,  88,  32,  and  77,  If  any  of  these numbers   are   not   displayed,   the   FAILURE/ACTION indicator  or  its  immediate  drive  circuit  is  defective  and must  be  replaced.  The  sequence  does  not  function  if  the buffer  unit  is  looped  back  for  self-test,  In  addition,  the LAMP  test  switch  lights  all  other  SPU  indicators  except ENTER  and  LAMP  TEST. (3)  SPU  BITE  start-up  circuitry  for  the  tape reader.  When  the  SPU  SELF  TEST  switch-indicator  is activated,   the   tape   reader   will   be   sent   a   run   and   for- ward   signal.   When   these   signals   are   sent   to   the   tape reader,  they  will  also  be  monitored  by  redundant  circui- try  in  the  SPU.  Similarly,  known  test  data  read  by  the tape  reader  is  monitored  and  compared  to  the  expected values.   The   self-test   tape   will   have   test   characters spaced   periodically.   Whenever   a   test   character   is   read successfully  (as  determined  by  redundant  monitoring circuitry),  a  time-out  counter  will  be  reset,  and  testing will  continue.  If  the  time-out  counter  is  not  reset,  a malfunction   will   be   indicated.   By   spacing   test   charac- ters   on   the   tape,   a   rewind   to   the   start   of   tape   is   not necessary  whenever  self-test  is  stopped  and  then  re- started,   If   both   halves   of   the   redundant   monitoring circuitry  in  the  SPU  are  not  exactly  the  same,  the  SPU is  bad  and  not  the  tape  reader,  If  both  halves  indicate  a failure,   the   tape   reader   is   determined   to   be   faulty.   In such  a  case,  a  special  code  is  displayed  on  the  FAIL- URE/ACTION  indicator  on  the  SPU. 6-10