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Table 6-3. Input/Output Discrete Signals | Up
TM-5-6675-238-14 Theodolite: Directional: 0.002-MIL Graduation: 5.9 In. Long Telescope Detachable Tribrach: w/Accessories and Tripod Manual | Next
Teletypewriter Control Logic |
ARMY TM 5-6675-238-14
MARINE CORPS TM 08839A-14/1
Table 6-3. Input/Output Discrete Signals - Continued
Bit in
input
Output
Output discrete
discrete
Input discrete
group no.
signal name
word
signal name
Notes
3
IMU (to CDU)
+ 5V
115 VAC 90
Spare
+ 24V aux
Spare
S p a re
IMU flag set
4
Spares (not pres-
)
ently used
3
4
5
6
7
11
8
None
IMU ready
Accelerometer
coarse
heater on
Gyro coarse
heater on
Gyro float to
temperature
Spare no. 1
Spare no. 3
S p a r e
IMU fail
(from IMU)
The + 5V and 115 VAC must be moni-
tored to their own returns, The + 24V
aux must be monitored relative to its
common return. The IMU flag set signal
is sent from the computer to the SPU,
then sent back to the computer as the
IMU fail (from IMU) signal, then sent
back to the SPU as the IMU (to CDU)
signal, then finally sent back to the com-
puter as the IMU ready signal. The com-
puter program must compare the IMU
flag set signal that is sent from the com-
puter with the IMU ready signal that is
received from the SPU
are used for data control and for character parity. Parity
is checked for each character. A parity error causes the
tape reader to stop. The tape will stop on the character
in error. The first four tape characters are multiplexed,
four bits at a time, into the 16-bit data register. When
the 16-bit data register is full, that data is used to preset
a binary address counter if the data is an address word.
The address word is then multiplexed into the DMA
circuitry, If the data is not an address word, the 16-bit
data register contents are multiplexed as data bits into
the DMA control circuitry. At the end of the DMA
request signal, the binary address counter is advanced
by one count and the next DMA cycle is started. The
contents of the binary address counter are used as the
current memory address to be filled or verified. Each
DMA cycle requires an address followed by 16 bits of
data, If the current mode is one of filling memory, the
data in the 16-bit data register will be loaded into
memory. If the process is a memory verification, a
memory read cycle will be initiated. Filling memory is
initiated by activating the MEMORY LOAD switch-
indicator on the SPU front panel. This switch assures
that the read/input line to the DMA control circuits in
the computer will be in the input condition. When the
MEMORY LOAD switch-indicator is deactivated and
the VERIFY switch-indicator is activated, the same
sequence of events as described above occurs, except
that the read/input line to the DMA is in the read
condition. This causes the DMA control circuits in the
computer to read from the computer memory and input
the data to the SPU. In the SPU, each DMA input word
is compared to the word reread from the tape. If the
two words do not agree, the VERIFY ERROR indicator
is activated and the tape reader is stopped.
j. Teletypewriter Control Logic. The teletypewriter
control logic is functionally illustrated in figure FO-9
and is contained on logic no. 1 electronic component
assembly Al. The SPU is directly compatible with
Teletype Model ASR 32 (Baudot code), The teletype-
writer must be internally wired for full duplex opera-
tion, making possible simultaneous two-way communi-
cation. Since the teletypewriter interface is serial, both
serial-to-parallel and parallel-to-serial converters are
6-8
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