Table 6-1. Serial Data Bus Signals

ARMY TM 5-6675-238-14 MARINE CORPS TM 08839A-14/1 Table 6-1. Serial Data Bus Signals Signal name Characteristic Address/data Two-wire serial lines carrying 16-bit serial addresses or 16-bit serial data are either received in the SPU by a differential receiver, or are sent from the SPU by a differential tri-state driver. Either a 16-bit serial address or 16-bit serial data can be received by the SPU. 16-bit serial data can be sent by the SPU. All sent or received information is gated with the clock signal Clock A differential 250-kHz signal from the computer. Used to synchronize all information and control lines Data envelope Differential control lines from the computer. When the data envelope signal is in the one state, the information on the address/data lines is interpreted by the SPU as data Address envelope Differential control lines from the computer. When the address envelope signal is in the one state, the address/data lines represent address information SPU by the computer immediately following the ad- dress word. The data word is converted into either resolver or synchro signals and routed back to the computer on parallel data lines. f. Computer Discrete Loop Closer. The computer discrete loop closer is functionally illustrated in figure 6-2 and is contained on logic no.3 electronic compon- ent assembly A3. The IMU discrete signal lines are tested by the computer by loop closing logic in the SPU. Since there are more computer output discretes than input discretes, the output discretes must be multi- plexed onto the input discrete lines for the test. Output discrete groups 1, 2, 3, and 4 (refer to table 6-3) are applied to line receivers, then multiplexed and sent back to the computer from line drivers as input discrete lines 1 through 8 (refer to table 6-3). The multiplexing is under control of the computer serial data bus. The status of the output discrete lines is entered into the computer as bits in the input discrete word. Each line is directly monitored by the computer. For computer protection, no SPU synchro or resolver outputs to the computer can be present until the computer +5V is detected. g. Fail Discrete Status and On/OFF-Enter Logic. The fail discrete status and on/off-enter logic is func- tionally illustrated in figure FO-7 and is contained on logic no. 3 electronic component assembly A3 and the SPU front panel. The SPU takes the place of the CDU whenever a CDU is not present. Since the fail indicators must operate when all prime system power fails, they are powered by an auxiliary 24-VDC source in the PADS power supply. The 24-VDC is converted to V lamp in the computer and is then used in the CDU to power the COMP and IMU indicators. The SPU has its own power source during prime equipment checkout so drivers are used in the SPU to drive the COMP FAIL and IMU FAIL indicators. The ON/OFF and ENTER switches in the SPU are connected to simulate the ON/ OFF and ENTER switches in the CDU. This enables the SPU to turn on the computer when a CDU is not present. These switches supply a momentary ground to circuitry in the computer. The switches have anti- bounce circuitry associated with them. h. Tape Reader Control Logic. The SPU controls the tape reader with frent panel switches. The SPU also supplies all power to the tape reader via a front panel connector. The tape reader is bidirectional in operation, Forward and reverse direction of the tape reader is controlled by the SPU MEMORY LOAD and RE- VERSE switch-indicators respectively. i. Memory Load and Verify Logic. The memory load and verify circuits are functionally illustrated in figure FO-8 and are contained on logic no. 1 electronic component assembly Al. The SPU utilizes the tape reader to fill and verify computer memory. The fill and verify functions are under hardware control in the SPU and are also under hardware control in the computer via the direct memory access (DMA) bus. Data is loaded into memory, a word at a time, and each word transfer is done via a complete DMA input cycle. The loaded data is then verified by comparing each word which is read back from memory, via a complete DMA output cycle, to the data being reread from the punched tape. Five tape American Standard Code for Information Interchange (ASCII) characters are required to load a single 16-bit memory word. The fifth tape character identifies the first four characters as being addresses or data information. Each character uses four data bits per character as information to be loaded sequentially into a 16-bit register. The remaining four bits per character 6-3