ARMY TM 5-6675-238-14 MARINE CORPS TM 08839A-14/1 CHAPTER 6 FUNCTIONING OF EQUIPMENT Section  I.  HARDWARE  DESCRIPTION 6-1. General. This section describes the function of the PADS test set. An overall general block diagram de- scription is given, then detail descriptions are given for each functional section. A block diagram and functional block diagrams are included where necessary to support the  text. 6-2. PADS Test Set Function.  The PADS test set is capable of automatically testing the PADS computer input/output signals. A block diagram of the PADS test set is shown in figure FO-1. Communication with the computer is via the serial data bus, IMU simulation, CDU simulation, and direct memory access/CPU bus. The buffer unit is required between the SPU and com- puter for conditioning of the direct memory access and teletypewriter  communication  signals.  The  computer serial data bus has control over the SPU serial data bus control  logic  for  decoding  computer  signals  at  the proper  times.  The  serial  data  bus  control  logic  has control over all loop closer circuits (except           This activates these circuits for a transmit or receive mode  of  operation.  When  the  serial  data  bus  loop closer has been activated, it receives an address word from the computer. The address is decoded and trans- mitted  back  to  the  computer  as  an  inverted  address word.  IMU  simulation  signals  representing  gyro  torqu- ing  are  sent  from  the  computer  to  the              loop closer. These signals are converted to velocity signals and sent back to the computer. The clock generator in the               loop closer provides synchronization within this section. The clock generator also supplies a clock pulse to the computer to synchronize various functions. The               loop closer runs continuously in response to  computer  signals  from  the  IMU  simulation  bus,  and is not under serial data bus control. The computer sends a digital word to the digital/DC loop closer for conver- sion to an analog signal. This analog signal is routed back to the computer for a comparison check to ensure that the computer is functioning correctly in this area. An angle data word from the computer is sent to the digital/resolver  and  digital/synchro  loop  closer  for conversion to a resolver or synchro signal. The con- verted signal is routed back to the computer where it is reconverted to digital and compared to the angle that was sent, The computer discrete loop closer is used to close  the  discrete  line  loop  between  the  SPU  and computer. This allows the computer to test the IMU discrete   signals. a.  The  SPU  can  be  used  with  or  without  a  CDU connected to the computer. For the SPU to perform the CDU functions, a fail discrete status and on/off-enter logic  has  been  incorporated  in  the  SPU.  This  logic circuit  provides  on/off,  enter,  and  fail  status  for  the computer in the absence of a CDU. b.  The  SPU  supplies  all  power  and  control  func- tions to the tape reader. The tape reader is utilized for computer  memory  fill  and  verify.  The  memory  fill  and verify function processes data from the tape reader tape that is to be loaded into the computer memory via the direct memory access bus. The data is then verified to ensure that it was loaded into memory correctly. During self-test, the tape reader provides data from a self-test tape to exercise the various functions within the SPU. c. The teletypewriter communicates with the com- puter via the SPU teletypewriter control circuitry and computer  data  bus.  The  teletypewriter  control  circuitry converts teletypewriter serial data to parallel data for transmission to the computer. Computer parallel data sent to the teletypewriter is converted to serial data by the teletypewriter control circuitry. d. Provided within the SPU is a built-in test equip- ment  (BITE)  circuit  permitting  a  self-test  to  be  per- formed. When self-test is activated, the various func- tional sections in the SPU are exercised by data from a self-test    tape. e.  Power  supplies  in  the  SPU  generate  +5,  +  15, +28, and -15V. All these voltages are used in the SPU, + 28V is used in the tape reader, and + 5V is used in the  buffer  unit  during  self-test. 6-3. Signal Processor Unit Function. The SPU contains the following functional circuits: serial data bus control logic, serial data bus loop closer,          loop closer, digital/dc  loop  closer,   digital/resolver   and   digital/ synchro loop closer, computer discrete loop closer, fail discrete status and on/off-enter logic, tape reader con- trol logic, memory load and verify logic, teletypewriter control  logic,  built-in  test,  and  power  supplies.  The following  paragraphs  briefly  describe  each  function. a. Serial Data Bus Control Logic.  The serial data bus control logic is functionally  illustrated  in  figure  FO- 2 and is contained on logic no. 3 electronic component 6-1