READ/WRITE CONTROL

USART chip (fig. 7-18) is composed of logic circuits, which are connected by an internal data bus. The logic circuits are read/write control logic, modem control, data bus buffer, transmit buffer, transmit control, receive buffer, and receive control. The CPU communicates with the USART over an 8-bit bidirectional tristate data bus. The USART is programmable, meaning the CPU can control its mode of operation using data bus control and command words. The read/write control logic then controls the operation of the USART as it performs specific asynchronous interfacing. READ/WRITE CONTROL. —The read/write control logic accepts control signals from the control bus and command or control words from the data bus. The USART is set to an idle state by the RESET signal or control word. When the USART is IDLE, a new set of control words is required to program it for the applicable interface. The read/write control logic receives a clock signal (CLK) that is used to generate internal device timing. Four control signals are used to govern the read/write operations of the data bus buffer. They are as follows: The CHIP SELECT (CS) signal, when true, enables the USART for reading/writing operations. The WRITE DATA (WD) signal, when true, indicates the microprocessor is placing data or control words on the data bus to the USART. The READ DATA (RD) signal, when true, indicates the microprocessor is ready to receive data or status words from the USART. The CONTROL/DATA (C/D) signal identifies the write operation transfer as data or control words, or the read operation transfer as data or status words. MODEM CONTROL. —The modem control logic generates or receives four control or status signals used to simplify modem interfaces. They are as follows: Figure 7-18.—Universal synchronous/asynchronous receiver transmitter (USART). 7-20