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Instruction and Control Operations | Up
Fire Controlman Volume 03-Digital Data Systems | Next
INSTRUCTION OPERAND ADDRESSING |
Figure 5-7.—Basic operation of a fetch and decode (translate)
of an instruction in a CPU.
FETCH (READ) THE INSTRUCTION. —The
instruction is fetched by reading the instruction from the
memory (main memory or ROM) address specified by
the contents of the program counter or equivalent. The
instruction is temporarily stored in an instruction
register, while the program counter is being
incremented to the next instruction’s address.
UPDATE THE PROGRAM COUNTER. —The
program counter controls the selection of the
instruction. The program counter contains the memory
address of the next machine instruction to be executed.
Most of the time machine instructions are executed
sequentially. The program counter is incremented to
the address of the next instruction. Usually an index
adder is used to perform this function. When an
instruction is completed, the new count in the program
counter points to the next instruction to be fetched from
memory and executed in turn.
The memory word size of the computer has an
effect on the value that is used to increment the program
counter. For those computers in which the majority of
instructions are contained in one memory word, the
program counter is incremented by one (1) for each
instruction. For computers with smaller memory words
(8-bits), instructions are often assembled from several
sequential bytes and the program counter must be
incremented by a value that will point to the first byte
of the next instruction to ensure correct translation of
that instruction’s operation code.
There are times, however, when a change in the
sequence of instruction execution, called branching or
jumping, is required. Branching or jumping can be
accomplished through the man/machine interface by
using switches on the controlling consoles. Examples
Figure 5-8.—Block diagram of an operation to determine an
absolute address.
are the stop and jump switches. In these cases instead
of being incremented, the address in the program
counter is changed to anew address to start sequential
execution of a different section of machine instructions
in the program. Branching or jumping can also be
accomplished through program instructions.
In some computers, the program counter contains
the relative or offset address of the instruction being
executed. An additional set of registers called base
registers are used to provide the base address of a block
of memory. The program counter value must be added
to a selected base register value (fig. 5-8) to determine
the absolute address of the next sequential instruction.
TRANSLATE THE INSTRUCTION. —An
instruction register holds the machine instruction while
it is translated by other CPU logic (translators). The binary
data that makes up the instruction op code determines
the operation the CPU is to perform. The derived func-
tion codes are then sent to other parts of the control section
of the CPU to execute the instruction. The translation
of the instruction determines which command
sequences will be used to execute the instruction.
EXECUTE THE INSTRUCTION. —Execution
of the instruction will generate command enables that
are used throughout the computer to transfer data
between registers and other parts of the computer. The
logic consists of gating and amplifying circuits, which
produce or inhibit control signals appropriate to the
combination of conditions at their inputs. The
controlling conditions are supplied by the timing
circuits (master clock, main timing chains, and timing
sequences) and function code translator and associated
circuitry (selectors, registers, adders, and comparators).
An execution technique used in newer
microprocessors contains a logic assembly called an
instruction queue. It is used to speed up computer
operations and increase efficiency. The instruction
queue allows the microprocessor to fetch a number of
sequential instructions or instruction bytes and hold
them in a queue for execution by the execution unit of
the microprocessor. The instructions are fetched by the
bus when the memory section is available for access and
in some cases pretranslated while the processor is
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