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Page Title: Computer Interconnection System
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BUS TYPES
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Electronics Technician Volume 06-Digital Data Systems
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BUS OPERATIONS

memory at the address defined by the address bus or consists of data read from the memory address specified by the address bus. Figure 5-17 is an example of a computer’s bus system; control, address, and data buses. Instruction (I) Bus The instruction (I) bus allows communication between the CPU and memory. It carries to the CPU the program instruction words to be operated on by the CPU from memory or returns instructions to memory. The I bus is controlled by the CPU. It is capable of sending or receiving data while the operand(O) bus is receiving or sending data at the same time, but only in one direction at a time. Operand (O) Bus The  operand  (O)  bus  allows  communication between the CPU and memory or the CPU and an I/O Controller (IOC). The CPU controls the operation in both cases. The O bus is capable of sending or receiving data, while the I bus is receiving or sending data at the same time, but only in one direction at a time. The direction of the data depends on whether the CPU is reading data from memory or data is being written back into  memory. I/O MEM Bus or Input/Output Controller (IOC) BUS The  I/O  memory  bus  allows  communication between an I/O controller (IOC) and memory. It is Figure  5-17.—Example  of  a  computer’s  bus  system;  control, address,  and  data  buses. controlled by the IOC. To respond to the CPU, the I/O MEM bus must use the O bus. Figure 5-18 is an illustration of communications between  a  CPU,  memory,  and  an  IOC  without  a computer  interconnection  system.  Pay  close  attention to the direction of signal flow and which buses allow communication between functional areas. Computer Interconnection System The  Computer  Interconnection  System  (CIS) provides  the  complete  functional  replication  of  the computer  intraconnection  among CPUs, IOCs, and memories  in  separate  computers.  This  allows  the internal  buses  to  be  extended  beyond  their  own enclosure.  The  CIS  consists  of  two  independent  halves: the requestor extension interface (REI) and the direct memory interface (DMI). REQUESTOR  EXTENSION  INTERFACE (REI).— The requestor extension interface (REI) is a bus extender. It extends the bus up to 15 other computer cabinets  providing  an  interconnected  system  of memory modules, CPUs, and IOCs. The REI takes the requests from the requestor ports and goes through a priority network to determine the order in which it is to respond to the requestors. Once the REI has responded to a request, it puts the address onto the output bus, Figure  5-18.—Bus  system  between  a  CPU,  memory,  and  IOC without CIS. 5-25

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