Ratio Autoranging (A1 Assembly)

TM 11-6625-444-14-2

518. Ratio Up Range Detector,

5-16. Ratio Autoranging (A1 Assembly)

Minus Input Signal

In addition to the autoranging circuitry already

For the same ratio voltage conditions as given

discussed for voltage mode in paragraphs 5-9

in the previous paragraph, except a -90 V input

through 5-13, circuitry precedes it which is used

s i g n a l is applied, the signal present at the

for the ratio autoranging. To better understand

junction of RN401-2,15 and RN403-8,9 is -4.5

the sequence of autoranging in the RATlO mode,

V . A +5 V signal (reference) is present at

the following brief description is given. Refer to

RN403-9,10.

T h e voltage "summed" at the

schematic diagram, figure FO5.

junction of these two resistors is approx. 0 volts.

This level is applied to the non-inverting input of

5-17. Ratio Up Range Detector,

U402B.

Plus Input Signal

For the sake of discussion, the following ex-

The inverting input, pin 7, of U402B is adjust-

ample is for an input voltage of +90 V (on the

ed to be "0" volts by R404. If the input signal

200 V full scale range) and a reference voltage

then goes slightly more negative ( < -90 V), the

of 50 V. (Regardless of the polarity of the ap-

resulting signal at the input of U402B pin 6 will

plied reference voltage, it will be presented to

be slightly negative. This causes the op-amp to

the ratio up/down range detectors as a positive

swing towards the negative supply voltage of

voltage. ) This ratio has been chosen because it

- 1 5 V, again producing an "Up Range com-

is right at the threshold of up-ranging (>180,000

mand".

counts).

5-19. Ratio Down Range Detector,

Plus input Signal

When the RATIO mode is selected, a logic "low"

is present at 4 (figure FO-5) causing a "high"

at U403B, enabling it. This also presents a "low"

The following discussion uses the example of

at U403D pin 9, disabling it; thus preventing the

a +14 V input voltage (on the 200 V full scale

output of U405 from being "gated through" to

range) and a 100 V reference voltage. This ratio

U407.

has been selected because it is right at the

threshold of down-ranging ( c 14,000 counts).

An input of +90 volts to the voltage input ter-

minals will be attenuated by 40 dB to +0.9 volts

As in the up range situation, a +14 V input sig-

when on the 200 V range. The Dc Buffer Ampli-

nal is attenuated 40 dB on the 200 V range, to

fier then amplifies this signal by 5, increasing it

+0.14 volts. The Dc Buffer Amplifier then in-

to +4.5 volts. This voltage is next applied to pin

creases the gain of' the input signal by a factor

1, the inverting input of U402A.

of 5, to +0.7 V. Because the ratio down range

detector deals with low signal levels, the input

The 50 V ratio reference voltage, because it

signal is further amplified by 20 dB in U400. This

+7 V signal is now applied to the inverting input

exceeds 10.5 volts, is attenuated by 20 dB in

A9-U1 to +5 volts. Through the action of the

of U401A pin 1.

voltage divider comprised of RN401-1,16 and

RN403-1,7; the actual voltage presented to pin

The 100 V reference voltage is attenuated by

2 of U402A is also +4.5 V. When the level at pin

20 dB in the Dc Ratio Amplifier to become 10 V.

1 (input signal) increases to only a few millivolts

The divider action of RN401-3,14 and RN403-1,

higher than that at pin 2, the reference becomes

6 produces a +7 V reference input to the

negative with respect to the input signal causing

non-inverting input of U401A pin 2.

t h e output of U402A to swing towards the

negative supply voltage (-15 V). This results in

a "low" at the input of U403A (used as an in-

When the signal voltage drops to just below

+14 V, the resulting dc voltage at U401A pin 1

verter) and then a "high" at pin 3 of U403B. Pin

becomes slightly less than +7 V or, negative with

2 of U403B is also "high" because RATIO mode

respect to the reference voltage at pin 2. This

has been selected. This provides a "low" at the

causes the output of U401A to swing positive

output of this NAND gate which is the correct

towards the open collector supply voltage of +5

logic for an "Up Range command" to U406.

5-10