Table 5-1. Sample and Hold Switching

TM 11-6625-444-14-1

and C10. The sequence of operation for the sample

f. The sample and hold circuit consists of

and hold circuit is shown in table 5-1.

transistors Q25 through Q28 and capacitors C9

Table 5-1. Sample and Hold Switching

NOTE

Voltages shown are only proportional to actual voltages.

and the analog voltages stored on the storage

g. The ladder switches of Q37 through Q44 are

capacitors are serially applied to the input of the

controlled by drivers Q19 through Q22 on the

A/D amplifier. Thus, the same reading is con-

logic board (A8). The output of the ladder

tinually digitized and displayed until a new

switches is applied to two ladders. Each ladder

sample of the input is taken.

comprises a 4-bit, weighted-resistor, digital-to-

analog converter. The primary ladder consists of

i. The 333 Hz clock signal is produced by

resistors R44 through R50 and produces an

transistor Q1 on the logic board (A8). The clock

output that corresponds to the actual value of the

frequency is determined by the RC time constant

most significant digit of the A/D amplifier input

of resistor R1 and capacitor C1. The output of Q1

voltage. The secondary ladder, which drives only

is applied to the trigger input of flip-flop UIB.

the display storage circuit through buffer am-

The F output of UIB is inverted in Q4 and

plifier U3, consists of resistors R40 through R43

and produces an output that closely approximates

used by the logic to generate control signals.

the actual value of the primary ladder output. A

j. The six-state shift register consists of J-K

half-digit bias is produced by R38 and R39 in

flip-flops U3A, U3B, U4A, U4B, and UIA. Error

conjunction with the secondary ladder resistors

correction gate U2B controls the input to flip-flop

and adds the voltage equivalent of a half-digit to

U3B to insure proper operation of the shift

the output of the secondary ladder. This insures

proper display storage readout by compensating

flip-flop UIA reverts to the ZERO condition upon

for the effects of voltage decay in the storage

circuit.

now in the ZERO condtion; therefore, the output

h. The display storage circuit consists of FET

of U2B goes low, thereby defining the start of the

switches Q13 through Q17, capacitors C11

ZERO subperiod as shown in the timing diagram

through C15, and FET switches Q12 and Q18.

of figure 5-5 . The ZERO subperiod is ter-

The buffered output of the secondary ladder is

supplied to the appropriate storage capacitor

flip-flop U3B high because its J input was high

through Q18, which is switched on during the

and its K input was low when the clock pulse was

second half (display time) of each subperiod. The

received. Subsequent clock pulses set the flip-flop

first (most significant) digit is stored on C13, the

outputs as shown in table 5-2.

second on C11, etc. When the cycle change cir-

cuitry switches to storage mode, Q12 is turned on

5-8