Reference Supply

TM 11-6625-2616-14

Q2 as a common source load. Q9 and Q10 provide

5-9. Reference Supply

symmetrical loading for Q1 with Q8 providing an

unbalanced output. When the input integration

a. The reference supply (U24) incorporates

pulse appears at pin 5, Q6 is turned on, actuating

circuitry to provide the following functions:

Q4 and the clock gate amplifier externally con-

nected via pin 7. This allows the clock frequency

(1) Produce an accurate +10 volts which is

to start. Q6 also turns on Q5 simultaneously with

used as a reference for all the other regulated

Q4. Q5 functions to provide a path for the refer-

supplies.

ence current coming from the drain of constant

(2) Product an accurate reference current

current, source Q7 during integration time.

which is used to discharge the integrating capaci-

tor.

b. At the end of the integration period, Q6, Q4,

and Q5 switch off. Q3 senses the charge on Cl

(3) Electronically switch external reference

(through amplifiers Ql, Q8, and Q9 ) and keeps the

voltages of either polarity to a unipolar controlled

clock gate on. The reference discharge current

reference discharge current.

flows from the drain of Q7 through CR3, C12, and

b. Operational amplifier Ul, transistor Ql,

(C1, discharging Cl. When Q1 senses that C1 has

Zener CR1, and associated circuitry produce the

discharged, Q3 is turned on, permitting the cur-

accurate + 10-volt reference at pin 13. Amplifier

rent from Q7 to flow into pin 7 and control the

U2 and transistor Q2 produce the accurate refer-

clock gate amplifier Q28 and Q20 which stops the

500 KHz oscillator.

ence current which appears at pin 12.

Figure 5-7. Reference supply, simplified schematic

diagram.

5-9