Major Subsystems and System Buses cont'd

TM 11-7021-202-12

The two internal buses handle ail data exchanges between the subystems. The MEMIN bus

carries address and write data to the memory system and also carries information from the

CPU to the FPU. The bus is unidirectional and 21 bits wide, which permits physical

addressing of 2048k words in core memory systems and the transfer of 16-bit data words in

both semiconductor and core memory based systems. The illustration on the previous page

depicts a semiconductor-memory based system, which accommodates a 21-bit word (15

data bits, plus a 5-bit error code). In core-memory systems, a 17-bit word is stored (16 data

bits plus an odd parity bit). The MEMOUT bus is essentially a 16-bit unidirectional bus and

carries data and instructions read from memory to the CPU, programmed I/O information

and data from the CPU to the I/O interfaces, and floating-point information from the FPU to

the CPU. The I/O Bus interfaces with both of the memory buses for the purposes of direct

memory access and I/O transfers under CPU supervision.

The I/O bus carries all command and data transactions between the processor and

peripheral device interfaces. The transactions are of two types: Programmed I/O and Direct

Memory Access (DMA). Programmed I/O operations are initiated by the CPU to execute a

software instruction. The operation may involve a transfer of data to or from an I/O interface,

the transmission of a control command from the CPU to the device including functional

parameters, or the retrieval of the device status. DMA operation is initiated by the CPU, but

involves the transfer of data between the I/O interface and memory without CPU

intervention. For both programmed I/O and DMA transfers, 16 bidirectional data lines within

the I/O bus are used. The remaining lines within the bus are used for control and device

selection functions. A communications line connects the system terminal to the Universal

Asynchronous Receiver/Transmitter (UART) in the CPU. This line is dedicated to the system

terminal.

The CPU coordinates the operations of all the other subsystems by status and control lines.

The CPU executes all memory data references and instruction fetches by means of its

mapping logic, which translates a 15-bit or 16-bit logical address into a 20-bit physical

address, places the address on the MEM IN bus, and requests the appropriate memory

cycle.

The MAP logic checks for violation of one of several types of protection. If a violation is

detected, the CPU is notified and a protection trap ensues. If the memory cycle involves a

write-to-memory, the CPU places the data on MEMIN within specified timing constraints. If a

memory-read operation is involved, as in the case of an instruction fetch, the memory places

the data on the MEMOUT bus and the CPU takes the data from the bus at the specified

time.

After the CPU has received the data from an instruction fetch, the instruction is decoded

and the appropriate action is taken. If the instruction required memory references, the CPU

will execute them as described. Accumulator-to-accumulator operations, including fixed-point

arithmetic, are executed entirely within the CPU.

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