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Figure 1-3. Processor Front Panels		Up
TM-11-7021-202-12 Data Processing Set AN/UYK-64(V)1 (NSN 7035-01-155-0153) Manual		Next
Table 1-4. Data Processing Set AN/UYK-64 (V), Configuration Matrix

TM 11-7021-202-12
1-11.
DIFFERENCES BETWEEN MODELS
Table 1-4 provides a matrix depicting the eight various configurations (versions) of the
processor. Also, refer to paragraph 1-8.
1-12.
EQUIPMENT CONFIGURATIONS
The following paragraphs discuss the various configurations (versions) of the processor and
the system configurations in which the processor maybe deployed.
a.  Processor Configuration. The primary differences between one version of the
processor and any of the other seven versions are (table 1-4):
Type of power system (ac or dc).
q
Type of memory (core or semiconductor).
q
Model of CPU PROM PCB (P/N 109836-01 or 109836-04).
q
· Model of FPU-C PCB (FPU-CE, P/N 109836-01 or
FPU-C66, 11 0984-01).
Model of Motherboard Assembly (P/N 109884-01 or
q
109885-02); includes Front Panel Assembly.
The chassis configuration (P/N 110393-02 or 110815-02).
q
· Type of I/O PCB (appx G).
Of prime interest when considering processor configurations (versions) is the card cage. The
paragraph to follow discusses the configuration of the processors' card cage.
b.  Card Cage Configuration. The processor card cage consists of the core or
semiconductor memory section, FPU section, CPU section, and the I/O section.
Although the card cage contains eight I/O board slots, the type of I/O boards used can vary
considerably, according to the number and type of peripheral devices required in a specific
system configuration.
c.  Memory Configuration. The following subparagraphs discuss the processor
memory configurations.
(1) Semiconductor memory. The memory size in a semiconductor-based processor
is 256k Words. The word length is 21 bits, consisting of 16 data bits and a 5-bit error
correction code. The 5-bit error correction code is generated by the A16 ERCC PCB during
a memory-write cycle and is checked during a memory read-cycle. The memory cycle time is
increased only if an error is corrected. The error code is transparent to the CPU.
Semiconductor memory is volatile and cannot retain data integrity when there is a power
interruption of up to 60 minutes.
1-13

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