Receive Data cont'd

TM 11-5805-424-15/NAVELEX 0967-220-9013/TO 31W2-2G-41

amplifier NSA-1 is applied to 6-volt clamp Q19 that

signal in the high 1,800cycle-per-second (cps) channel;

produces a 0-volt to a -6 volt DC NEUTRAL signal to

for all other channels, this delay equalization is

AND gate GAI-3 in the receiver data output module.

unnecessary.

(1) With delay equalizer assembly A25A3 in

e. The output of AND gate GAI-3 is fed to AND

use, pin 26 of the MX-73(*)/G module is open and the

gate GAS-3, amplifier IN-12, and bistable FFA-1.

input signal is passed through the delay equalizer

(1) AND gate GAI-3 inverts the input data

module to second input amplifier Q2, Q16.

signal when a talk-request signal (para 5-23) is not

(2) If the delay equalizer assembly is not

applied to its second input. If a talk-request signal is

used, the input signal from resistor A9R3 is routed direct

applied to its second input, the output remains at a

to second input amplifier Q2, Q16.

constant negative level for the duration of the talk-

request signal, thus inhibiting all subsequent circuits. In

b. Second input amplifier Q2, Q16, a constant-

normal operation, a positive output from AND gate GAI-

current generator, matches the input characteristics of

3 triggers timing bistable FFA-1. When the bit-timing

receive filter FL1, which filters out all undesired

signal is applied in coincidence, negative output from

frequencies and provides only the correct channel

AND gate GAI-3, inverted by amplifier IN-12, is applied

frequencies (including the mark and space frequencies)

as a positive pulse to the S (set) input of bistable FFA-1.

to amplifier AM-5 in the demodulator module (c below).

Thus, bistable FFA-1 output is generated in accordance

The input signal is also applied through resistor A8R2 to

with the corrected bit-timing signal from the 128 divider-

third input amplifier Q15 in the receive input and carrier

B module (para 5-21) and provides a retimed output

alarm module for operation of the receive carrier alarm

data signal that is in synchronism with the master clock

signals (para 5-24).

timing.

c. The output of amplifier AM-5 is applied through

(2) The output of bistable FFA-1 is applied to

amplifier AM-6 to receive discriminator FL3 and to

AND gate GAD-2 and to strap terminal 3 at the input of

demodulator Q2-Q8, Q12-Q16.

the risetime and falltime shaper.

(1) Receive discriminator FL3 demodulates

(a) If straps 3 and 4 are connected, a

the fsk input signals, producing a dc output signal that

retimed (regenerated data signal is applied to the

contains the original transmitted data information. At

risetime and falltime shaper, which provides a sharply

the mark frequency, the phase shift from the

defined square-wave input for polar output data

discriminator is more than 900; a 90°shift is produced at

amplifier POD-1. Amplifier POD-1 supplies a polar

the center frequency. At the space frequency, the

output data signal with a +6volt mark bit, and a -6-volt

phase shift is less than 90° The shifted output signal

space bit.

from the discriminator is applied through isolation

amplifiers AM-7 and AM-8 to demodulator Q2-Q8, Q12-

(b) If an unregenerated receive data

Q16.

output signal is desired, terminal straps 2 and 4 are

connected so that recovered data is applied directly

(2) Demodulator Q2-Q8, Q12-Q16 compares

from amplifier IN-12 to the risetime and falltime shaper.

the fsk signals from amplifiers AM-5 and AM-8. Phase

relationships of the two signals applied to the

data

may

demodulator vary (on either side of 90°, causing the

)

automatically

switched

from

regenerated

demodulator output pulse to vary in duty cycle. The

nonregenerated through the talk-request facility as

average dc level at the output of the demodulator

described in paragraph 5-23. If the data output signal is

represents the recovered data signal.

to be regenerated terminal straps 1 and 4 are connected

together. In this case, AND gate GAD-2 is enabled and

d. The demodulator output is applied to post

applies the regenerated signal from bistable FFA-1

detection filter FL3, which blocks the carrier center

through the hidden OR gate to the risetime and falltime

frequency and applies the resultant dc signal (containing

shaper. If the data output signal is unregenerated, AND

the mark and space information) to nonsaturating

gate GAD-4 is enable and applies the recovered data

amplifier NSA-1 which acts as a slicer, to limit output

signal

signal levels. Polar output signal from nonsaturating

Change 5

5-24