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Page Title: Figure 5-4. Two-input bistable stage, +6-volt clamped output, schematic diagram and logic symbol
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Figure 5-2. Two-input bistable stages schematic diagram and logic
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TM-11-5805-424-15 Modem Low Speed Wire Line MD-674(P)/G Manual
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Figure 5-5. AND gate stages, schematic diagram and logic symbol.

TM 11-5805-424-15/NAVELEX 0967-220-9010/TO 31W2-2G-41
Figure 5-4. Two-input bistable stage, +6-volt clamped output, schematic diagram and logic symbol
Rb). Resistor Ra serves as a limiting resistor. If
type (d above), except that when the FFB-type
either input is a high level (ground), the
transistors conduct, the output is held at +6 volts instead
applicable diode conducts, providing a high
of ground, and no limiting resistor is used in the input
level (ground) at the output, with resistor Rb
circuit of transistor Qb.
dropping the 15 volts from the supply.
5-8. AND Gate Stages
(2) In the GAS-type AND gate (B, fig. 5-5),
(fig. 55)
capacitor Ca differentiates its input square wave,
and diode CRa passes only the positive spike if
the input to resistor Ra is also a high level. If
a. General.  Four basic variations of AND gate
the input to resistor Ra is a low level, capacitor
stages are used in the equipment. Two are inverting
Ca can never charge above ground and no
gates and two are noninverting gates.  Since the
output is available.
function of the stages is essentially the same, the same
(3) Two GAI-types of AND gate are used in the
basic logic symbol is assigned every stage. Differences
equipment.
in the logic symbols denote whether the required inputs
to activate the stage are low level (circle at the inputs of
(a) The type shown in C, figure 5-5, requires
the logic symbol) or high level (no circle at the inputs),
two high-level inputs (ground) to hold
and whether the activated (enabled) output is low level
transistor Qa cut off, providing a low-level
(circle at the output of the logic symbol) or high level (no
(-15 volts) output. A low level applied to
circle at the output).
either input is passed by its appropriate
diode (CRa  or CRb) to the base of
b. Circuit Analysis. An AND gate will develop a
transistor Qa, turning Qa on and providing
proper output when coincident input pulses of the same
a high-level (ground) output. Resistors Ra
polarity are present on the input lines.
and Rb  provide  initial  bias  for  the
(1) The GAD-type AND gate (A, fig. 5-5) requires
transistors. Resistor Rc
the two low-level inputs which are blocked by
diodes CRa and CRb, in order to provide a low-
level output (no current flows through resistor
Change 5
5-7

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