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Figure 1-25. Power Flow Block Diagram | Up
TM-55-4920-401-13P Test Set Fuel Quantity Gage Capacity Type P/N 361 010 002 Manual | Next
Figure 1-27. Quad 2 Input NOR Gate. |
TM 55-4920-401-13&P
( b ) I n t e g r a t e d C i r c u i t P i n L o -
cations of integrated circuits.
cations. Figure 1-26 shows top views and pin lo-
F i g u r e 1 - 2 6 . I n t e g a t e d C i r c u i t P i n L o c a t i o n s.
(c) Definitions of Logic Circuits.
Q outputs. The logic level present at the D input is
1 . Q u a d 2 - I n p u t N O R G a t e
transferred to the Q output during the positive-
(CD4001A). If one or both inputs of a single gate
going transition of the clock pulse (table 1-2). Set-
(fig. 1-27) are at the 1 logic level, the output will be
ting or resetting is independent of the clock and is
at the 0 logic level. If both inputs are at the 0 logic
accomplished by a high level on the set or reset line,
level, the output will beat the 1 level. The input and
respectively.
output relationships of a NOR gate are expressed in
3.
Triple
3-Input
NAND
Gate
“truth” table 1-1.
(CD4023AE). If all inputs of a single gate (fig. 1-
2 . D u a l
D - T y p e
F l i p - F l o p
29) are at the 1 logic level, the output will be at the
(CD4013AE). Each flip-flop (fig. 1-28) has inde-
0 level (table 1-3). If one or more inputs are at the 0
pendent data, set reset, and clock inputs and Q and
level, the output will be at the 1 level.
1-27
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